{"schemaVersion":"jobsearcher.job.v1","id":"207818dcf9d39f96a9952531","url":"https://jobsearcher.com/jobs/207818dcf9d39f96a9952531","canonicalUrl":"https://jobsearcher.com/jobs/207818dcf9d39f96a9952531","title":"Memory Debug Engineer","description":"Job Details Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world‑changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.\nWho We Are Client Customer Engineering Organization delivers hands‑on engineering partnership to PC OEMs, helping them design, validate, and launch next‑generation client platforms. We work closely with partners to integrate next‑gen Intel IA silicon and software, enabling innovative technologies and AI‑powered PC experiences.\nWho You Are As a Memory Debug Engineer within the Client Customer Engineering team, you will drive the enablement, validation, and complex debugging of memory subsystems for next‑generation Intel IA‑based Mobile and Desktop platforms. You will provide strategic oversight of memory I/O interfaces, ensuring they meet rigorous electrical performance and stability standards at POR target frequencies.\nKey Responsibilities Define and execute the overarching validation and debug strategy for memory I/O interfaces to achieve optimized functional and electrical performance to hit critical production milestones.\nLead the reproduction and root‑cause analysis of high‑priority customer‑submitted failure sightings, overseeing component‑level debugging within memory subsystems and driving data‑driven solutions through deep log analysis.\nEnsure all customer memory I/O interfaces meet industry‑standard electrical signal integrity (SI) compliance and maintain robust system‑level margins for stable operation at maximum POR frequencies.\nDefine Memory Reference Code (MRC) requirements for validation and margin optimization, analyzing and optimizing MRC steps and values to maximize product quality and reliability.\nAct as the primary liaison between Intel Silicon Engineering, BIOS/Firmware teams, and customers to resolve architectural bottlenecks.\nDemonstrate leadership in managing and driving task‑force environments to resolve critical bugs.\nEffectively translate complex electrical eye‑diagram issues into executive‑ready insights and recommendations, communicating with cross‑functional teams and external customers.\nQualifications Minimum Education: BS/MS/PhD in Electrical Engineering or Computer Engineering.\nMinimum Qualifications 4+ years of industry experience.\n3+ years of experience with DDR4/DDR5, LPDDR4/5 protocols and physical layer functionality.\n3+ years of experience with debug tools: high‑speed oscilloscopes, logic analyzers, margining tools, profilers (e.g., Intel Vtune), and protocol exercisers.\nPreferred Qualifications Knowledge of Intel‑specific debug tools (ITP, Scan, VISA) and mastery of the Intel System Debugger.\nExperience in JEDEC committees or familiarity with emerging standards such as CXL.\nProficiency in Python for developing automated debug scripts and data visualization tools.\nJob Type Experienced Hire\nShift Shift 1 (United States of America)\nPrimary Location US, Oregon, Hillsboro\nAdditional Locations US, California, Folsom\nBusiness Group Silicon and Platform Engineering Group (SPE)\nPosting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust N/A\nBenefits We offer a total compensation package that ranks among the best in the industry, consisting of competitive pay, stock bonuses, and benefit programs including health, retirement, and vacation. Annual salary range for US: $141,910.00 - $269,100.00 USD.\nWork Model for this Role This role requires an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.\nAdditional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment or medical examination fees as a condition of employment. If you are asked to pay any fees during the hiring process, please report this immediately to your recruiter.\n\n#J-18808-Ljbffr","company":"SupportFinity","rawCompany":"supportfinity","city":"Hillsboro","state":"IL","isRemote":false,"isActive":false,"createdAt":"2026-06-20T05:00:32.482Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Memory Debug Engineer","description":"Job Details Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world‑changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.\nWho We Are Client Customer Engineering Organization delivers hands‑on engineering partnership to PC OEMs, helping them design, validate, and launch next‑generation client platforms. We work closely with partners to integrate next‑gen Intel IA silicon and software, enabling innovative technologies and AI‑powered PC experiences.\nWho You Are As a Memory Debug Engineer within the Client Customer Engineering team, you will drive the enablement, validation, and complex debugging of memory subsystems for next‑generation Intel IA‑based Mobile and Desktop platforms. You will provide strategic oversight of memory I/O interfaces, ensuring they meet rigorous electrical performance and stability standards at POR target frequencies.\nKey Responsibilities Define and execute the overarching validation and debug strategy for memory I/O interfaces to achieve optimized functional and electrical performance to hit critical production milestones.\nLead the reproduction and root‑cause analysis of high‑priority customer‑submitted failure sightings, overseeing component‑level debugging within memory subsystems and driving data‑driven solutions through deep log analysis.\nEnsure all customer memory I/O interfaces meet industry‑standard electrical signal integrity (SI) compliance and maintain robust system‑level margins for stable operation at maximum POR frequencies.\nDefine Memory Reference Code (MRC) requirements for validation and margin optimization, analyzing and optimizing MRC steps and values to maximize product quality and reliability.\nAct as the primary liaison between Intel Silicon Engineering, BIOS/Firmware teams, and customers to resolve architectural bottlenecks.\nDemonstrate leadership in managing and driving task‑force environments to resolve critical bugs.\nEffectively translate complex electrical eye‑diagram issues into executive‑ready insights and recommendations, communicating with cross‑functional teams and external customers.\nQualifications Minimum Education: BS/MS/PhD in Electrical Engineering or Computer Engineering.\nMinimum Qualifications 4+ years of industry experience.\n3+ years of experience with DDR4/DDR5, LPDDR4/5 protocols and physical layer functionality.\n3+ years of experience with debug tools: high‑speed oscilloscopes, logic analyzers, margining tools, profilers (e.g., Intel Vtune), and protocol exercisers.\nPreferred Qualifications Knowledge of Intel‑specific debug tools (ITP, Scan, VISA) and mastery of the Intel System Debugger.\nExperience in JEDEC committees or familiarity with emerging standards such as CXL.\nProficiency in Python for developing automated debug scripts and data visualization tools.\nJob Type Experienced Hire\nShift Shift 1 (United States of America)\nPrimary Location US, Oregon, Hillsboro\nAdditional Locations US, California, Folsom\nBusiness Group Silicon and Platform Engineering Group (SPE)\nPosting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust N/A\nBenefits We offer a total compensation package that ranks among the best in the industry, consisting of competitive pay, stock bonuses, and benefit programs including health, retirement, and vacation. Annual salary range for US: $141,910.00 - $269,100.00 USD.\nWork Model for this Role This role requires an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.\nAdditional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment or medical examination fees as a condition of employment. If you are asked to pay any fees during the hiring process, please report this immediately to your recruiter.\n\n#J-18808-Ljbffr","datePosted":"2026-06-20T05:00:32.482Z","dateModified":"2026-06-20T05:00:32.482Z","hiringOrganization":{"@type":"Organization","name":"SupportFinity","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hillsboro","addressRegion":"IL","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"207818dcf9d39f96a9952531"},"url":"https://jobsearcher.com/jobs/207818dcf9d39f96a9952531"}}