{"schemaVersion":"jobsearcher.job.v1","id":"1fca0843ec381a81a5e1f708","url":"https://jobsearcher.com/jobs/1fca0843ec381a81a5e1f708","canonicalUrl":"https://jobsearcher.com/jobs/1fca0843ec381a81a5e1f708","title":"SoC Validation Engineer_ Pre & Post-Silicon","description":"*Mandatory ask*\n\n* Server level ASIC/SOC/silicon validation in either Pre or Post silicon environment\n* 10+ Years of experience\n* Experience with networking ASIC is a plus\n\n*Summary*\n\nWe are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems — including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs — with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.\n\n*Key Responsibilities*\n\n*Pre-Silicon Validation*\n\n* Develop comprehensive verification and validation plans for SoC-level IP subsystems including *Clock Generation/Distribution (PLLs, clock muxes, dividers)*, *Reset Architecture*, *Ethernet MAC/PHY*, and *I/O interfaces (GPIO, I2C, SPI, UART, JTAG)*\n* Create and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level\n* *Verify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior*\n\n* Validate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces\n* Perform functional coverage analysis *and drive coverage closure across IP blocks*\n* *Collaborate with design and architecture teams on RTL debug, assertions, and specification reviews*\n* Execute validation on emulation/FPGA prototyping platforms *(Palladium, Veloce, Protium) for early software/firmware integrationPost-Silicon Validation*\n\n* Bring up and validate SoC IPs on first silicon and platform boards\n* Develop and execute post-silicon test plans covering:\n* *Clock:* PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions\n* *Reset:* Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection\n* *Ethernet:* Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping\n* *I/O:* Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routing\n* Debug silicon failures using *oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx*, and embedded trace tools\n* Perform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams\n* Characterize IP performance under varying voltage, frequency, and temperature (VFT) conditions\n* Develop and maintain *automated test frameworks* for regression and production testing\n* Collaborate with platform, firmware, BSP, and driver teams on system-level integration and debug\n\n*General*\n\n* Author and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases\n* Develop *Python/Perl/Tcl scripts* for test automation, log parsing, and result analysis\n* Participate in silicon bring-up triage, failure analysis, and bug review meetings\n* Mentor junior engineers and drive process improvements in validation methodology\n* Interface with IP vendors for third-party IP integration, compliance, and issue resolution\n\n*Required Qualifications*\n\n* *Education:* B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field\n* *Experience:* 4–10+ years in SoC validation (pre-silicon and/or post-silicon)\n* Deep understanding of *SoC architecture* and IP integration concepts\n\nPay: From $90.00 per hour\n\nExpected hours: 40.0 per week\n\nWork Location: On the road","company":"Excelon Solutions","rawCompany":"excelon solutions","city":"Sunnyvale","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-08-28T09:40:31.154Z","occupations":[{"code":"17-2112.02","title":"Validation Engineers","slug":"validation-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"SoC Validation Engineer_ Pre & Post-Silicon","description":"*Mandatory ask*\n\n* Server level ASIC/SOC/silicon validation in either Pre or Post silicon environment\n* 10+ Years of experience\n* Experience with networking ASIC is a plus\n\n*Summary*\n\nWe are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems — including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs — with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.\n\n*Key Responsibilities*\n\n*Pre-Silicon Validation*\n\n* Develop comprehensive verification and validation plans for SoC-level IP subsystems including *Clock Generation/Distribution (PLLs, clock muxes, dividers)*, *Reset Architecture*, *Ethernet MAC/PHY*, and *I/O interfaces (GPIO, I2C, SPI, UART, JTAG)*\n* Create and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level\n* *Verify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior*\n\n* Validate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces\n* Perform functional coverage analysis *and drive coverage closure across IP blocks*\n* *Collaborate with design and architecture teams on RTL debug, assertions, and specification reviews*\n* Execute validation on emulation/FPGA prototyping platforms *(Palladium, Veloce, Protium) for early software/firmware integrationPost-Silicon Validation*\n\n* Bring up and validate SoC IPs on first silicon and platform boards\n* Develop and execute post-silicon test plans covering:\n* *Clock:* PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions\n* *Reset:* Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection\n* *Ethernet:* Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping\n* *I/O:* Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routing\n* Debug silicon failures using *oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx*, and embedded trace tools\n* Perform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams\n* Characterize IP performance under varying voltage, frequency, and temperature (VFT) conditions\n* Develop and maintain *automated test frameworks* for regression and production testing\n* Collaborate with platform, firmware, BSP, and driver teams on system-level integration and debug\n\n*General*\n\n* Author and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases\n* Develop *Python/Perl/Tcl scripts* for test automation, log parsing, and result analysis\n* Participate in silicon bring-up triage, failure analysis, and bug review meetings\n* Mentor junior engineers and drive process improvements in validation methodology\n* Interface with IP vendors for third-party IP integration, compliance, and issue resolution\n\n*Required Qualifications*\n\n* *Education:* B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field\n* *Experience:* 4–10+ years in SoC validation (pre-silicon and/or post-silicon)\n* Deep understanding of *SoC architecture* and IP integration concepts\n\nPay: From $90.00 per hour\n\nExpected hours: 40.0 per week\n\nWork Location: On the road","datePosted":"2026-08-28T09:40:31.154Z","dateModified":"2026-08-28T09:40:31.154Z","hiringOrganization":{"@type":"Organization","name":"Excelon Solutions","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"1fca0843ec381a81a5e1f708"},"url":"https://jobsearcher.com/jobs/1fca0843ec381a81a5e1f708"}}