{"schemaVersion":"jobsearcher.job.v1","id":"1d8a653ef04201a879471b4d","url":"https://jobsearcher.com/jobs/1d8a653ef04201a879471b4d","canonicalUrl":"https://jobsearcher.com/jobs/1d8a653ef04201a879471b4d","title":"ASIC Engineer, Implementation - Timing","description":"Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads at scale. As an ASIC Engineer focused on Implementation, you will drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets aggressive PPA targets for Meta's next-generation infrastructure platforms.\n\nASIC Engineer, Implementation - Timing Responsibilities:\n\nDevelop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks\nDevelop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes\nPerform STA for full chip and Physical partition blocks using PrimeTime\nRun Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power\nDeveloping Automation scripts and Methodology for all FE-tools including ( Synthesis, STA)\nWork closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks\nInteract with Physical Design Engineers and provide them with timing/congestion feedback\n\nMinimum Qualifications:\n\nBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience\nBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience\n6+ years of experience with Timing Analysis\nExperience with developing full chip flat & hierarchical timing constraints\nExperience with AOCV/POCV timing analysis , SI noise analysis\nExperience with running Static Timing Analysis for full chip using DMSA\nKnowledge of front-end and back-end ASIC flows\nExperience with communicating across functional internal teams and vendors\n\nPreferred Qualifications:\n\nExperience with SOC Design Integration & Front End Implementation\nExperience with Back End PD tools such as Fusion Compiler, Innovus\nExperience with Front End Synthesis tools such as Design Compiler, Genus\n\nAbout Meta:\n\nMeta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.\n\nMeta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.\n\nMeta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.\n\n$146,000/year to $209,000/year + bonus + equity + benefits\n\nIndividual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.","company":"Meta","rawCompany":"meta","city":"Austin","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-08-03T10:18:58.841Z","occupations":[{"code":"15-1299.08","title":"Computer Systems Engineers/Architects","slug":"computer-systems-engineers-architects"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"541715","title":"Research and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)","slug":"research-and-development-in-the-physical-engineering-and-life-sciences-except-nanotechnology-and-biotechnology"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"ASIC Engineer, Implementation - Timing","description":"Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads at scale. As an ASIC Engineer focused on Implementation, you will drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets aggressive PPA targets for Meta's next-generation infrastructure platforms.\n\nASIC Engineer, Implementation - Timing Responsibilities:\n\nDevelop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks\nDevelop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes\nPerform STA for full chip and Physical partition blocks using PrimeTime\nRun Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power\nDeveloping Automation scripts and Methodology for all FE-tools including ( Synthesis, STA)\nWork closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks\nInteract with Physical Design Engineers and provide them with timing/congestion feedback\n\nMinimum Qualifications:\n\nBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience\nBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience\n6+ years of experience with Timing Analysis\nExperience with developing full chip flat & hierarchical timing constraints\nExperience with AOCV/POCV timing analysis , SI noise analysis\nExperience with running Static Timing Analysis for full chip using DMSA\nKnowledge of front-end and back-end ASIC flows\nExperience with communicating across functional internal teams and vendors\n\nPreferred Qualifications:\n\nExperience with SOC Design Integration & Front End Implementation\nExperience with Back End PD tools such as Fusion Compiler, Innovus\nExperience with Front End Synthesis tools such as Design Compiler, Genus\n\nAbout Meta:\n\nMeta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.\n\nMeta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.\n\nMeta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.\n\n$146,000/year to $209,000/year + bonus + equity + benefits\n\nIndividual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.","datePosted":"2026-08-03T10:18:58.841Z","dateModified":"2026-08-03T10:18:58.841Z","hiringOrganization":{"@type":"Organization","name":"Meta","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"1d8a653ef04201a879471b4d"},"url":"https://jobsearcher.com/jobs/1d8a653ef04201a879471b4d"}}