Physical Design Engineer

Physical Design Engineer (Contract)Location: San JoseWe are seeking experienced Physical Design Engineers to support large-scale, timing-critical semiconductor designs at advanced technology nodes. This role will focus heavily on synthesis, floorplanning, implementation optimization, and early timing convergence for complex SoC and AI-class products.Key Responsibilities:Perform synthesis for large, timing-challenged designs using Cadence GenusDrive PPA (power, performance, and area) optimization throughout synthesis and early implementation stagesDevelop, refine, and optimize floorplans using Cadence InnovusCollaborate closely with RTL and architecture teams to provide feedback on design quality, constraints, and architectural tradeoffsPartner with internal and external P&R teams to improve timing closure and implementation convergenceIdentify and resolve timing bottlenecks early in the design flowSupport implementation strategies for advanced-node semiconductor productsContribute to methodology improvements and best practices for physical design flowsPreferred Qualifications:Minimum 5+ years of Physical Design experienceStrong experience with large-scale SoC, HPC, or AI accelerator designsHands-on expertise with advanced technology nodes such as N5, N3, or belowDeep understanding of timing closure, synthesis-to-implementation correlation, and PPA optimizationStrong hands-on experience with Cadence Genus and InnovusExperience working cross-functionally with RTL, architecture, PD, and external implementation teamsStrong debugging, problem-solving, and communication skills in fast-paced development environments