{"schemaVersion":"jobsearcher.job.v1","id":"1c5d4f8c3ee36b2e55632143","url":"https://jobsearcher.com/jobs/1c5d4f8c3ee36b2e55632143","canonicalUrl":"https://jobsearcher.com/jobs/1c5d4f8c3ee36b2e55632143","title":"Embedded FPGA Engineer","description":"Embedded FPGA Engineer\nJob Number: R0241391\n\nOpportunity\nWe are seeking a motivated FPGA and software engineer to support the development, optimization, and deployment of digital signal processing (DSP) functions on a SOSA/VPX system. As a member of our engineering team, you will design, implement, and validate system components. You will contribute to building RF signal processing applications on an embedded platform with cutting‑edge FPGAs. You should be comfortable with writing HDL, using Vitis HLS, and be willing to learn new development acceleration tools outside of traditional workflows.\n\nWhat You Will Do\n\nDesign and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains.\n\nDevelop and optimize DSP algorithms including filtering, detection, synchronization, modulation, demodulation, and transforms for high‑throughput and resource‑efficient hardware blocks.\n\nCollaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures.\n\nTest, verify, and validate FPGA designs, ensuring functional correctness, stability, and performance under real‑time constraints.\n\nOptimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows.\n\nDevelop reusable hardware IP blocks, enabling scalable DSP pipelines and accelerating future development.\n\nMaintain documentation, including design notes, block diagrams, interface definitions, user guides, and workflow references.\n\nContribute to innovation by identifying new techniques and technologies that improve FPGA development efficiency, DSP performance, or overall system capability.\n\nYou Have\n\n3+ years of experience developing FPGA or SDR solutions.\n\nExperience with Python, C++, MATLAB, or languages used for modeling DSP algorithms.\n\nExperience with Agile processes and tools, including Jira or Confluence.\n\nExperience with FPGA design using Verilog, VHDL, SystemVerilog, or HLS, and evaluation tools such as simulation, synthesis, fitting, timing analysis, implementation, and debugging.\n\nExperience with Xilinx, Vitis, Vivado, or FPGA development ecosystems and scripting such as Tcl.\n\nExperience with Linux/UNIX development environments and scripting languages.\n\nKnowledge of digital design fundamentals, streaming architectures, pipelining, buffering, and datapath timing.\n\nAbility to read hardware schematics and work with lab equipment, including logic analyzers, oscilloscopes, and spectrum analyzers.\n\nAbility to obtain a TS/SCI clearance.\n\nBachelor's degree in Electrical Engineering or Computer Engineering.\n\nNice If You Have\n\nExperience implementing or prototyping DSP algorithms in hardware.\n\nExperience with SOSA/VPX systems.\n\nExperience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation.\n\nExperience with porting and adapting vendor RF transceiver reference designs to FPGA evaluation boards and custom platforms.\n\nExperience with RF testing.\n\nExperience with high‑speed digital interfaces such as AXIStream, AXI‑Lite, DMA, and custom streaming buses.\n\nExperience with GPU acceleration, parallel computing, or high‑bandwidth data processing.\n\nExperience gathering requirements, shaping development roadmaps, or supporting Agile workflows.\n\nExperience with modern agile engineering workflows, including AI‑driven automation for FPGA design, simulation, synthesis, or testing.\n\nMaster's degree in Electrical Engineering, Computer Engineering, or a related field.\n\nClearance\nApplicants selected will be subject to a security investigation and may need to meet eligibility requirements for access to classified information.\n\nCompensation\nFull‑time and part‑time employees working at least 20 hours a week are eligible for Booz Allen's benefit programs. The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD). This posting will close within 90 days from the posting date.\n\nEqual Employment Opportunity\nAll qualified applicants will receive consideration for employment without regard to disability, status as a protected veteran or any other status protected by applicable federal, state, local, or international law.\n\n#J-18808-Ljbffr","company":"Phase2 Technology","rawCompany":"phase2 technology","city":"McLean","state":"VA","isRemote":false,"isActive":false,"createdAt":"2026-06-27T03:17:59.205Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"}],"industries":[{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334511","title":"Search, Detection, Navigation, Guidance, Aeronautical, and Nautical System and Instrument Manufacturing","slug":"search-detection-navigation-guidance-aeronautical-and-nautical-system-and-instrument-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Embedded FPGA Engineer","description":"Embedded FPGA Engineer\nJob Number: R0241391\n\nOpportunity\nWe are seeking a motivated FPGA and software engineer to support the development, optimization, and deployment of digital signal processing (DSP) functions on a SOSA/VPX system. As a member of our engineering team, you will design, implement, and validate system components. You will contribute to building RF signal processing applications on an embedded platform with cutting‑edge FPGAs. You should be comfortable with writing HDL, using Vitis HLS, and be willing to learn new development acceleration tools outside of traditional workflows.\n\nWhat You Will Do\n\nDesign and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains.\n\nDevelop and optimize DSP algorithms including filtering, detection, synchronization, modulation, demodulation, and transforms for high‑throughput and resource‑efficient hardware blocks.\n\nCollaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures.\n\nTest, verify, and validate FPGA designs, ensuring functional correctness, stability, and performance under real‑time constraints.\n\nOptimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows.\n\nDevelop reusable hardware IP blocks, enabling scalable DSP pipelines and accelerating future development.\n\nMaintain documentation, including design notes, block diagrams, interface definitions, user guides, and workflow references.\n\nContribute to innovation by identifying new techniques and technologies that improve FPGA development efficiency, DSP performance, or overall system capability.\n\nYou Have\n\n3+ years of experience developing FPGA or SDR solutions.\n\nExperience with Python, C++, MATLAB, or languages used for modeling DSP algorithms.\n\nExperience with Agile processes and tools, including Jira or Confluence.\n\nExperience with FPGA design using Verilog, VHDL, SystemVerilog, or HLS, and evaluation tools such as simulation, synthesis, fitting, timing analysis, implementation, and debugging.\n\nExperience with Xilinx, Vitis, Vivado, or FPGA development ecosystems and scripting such as Tcl.\n\nExperience with Linux/UNIX development environments and scripting languages.\n\nKnowledge of digital design fundamentals, streaming architectures, pipelining, buffering, and datapath timing.\n\nAbility to read hardware schematics and work with lab equipment, including logic analyzers, oscilloscopes, and spectrum analyzers.\n\nAbility to obtain a TS/SCI clearance.\n\nBachelor's degree in Electrical Engineering or Computer Engineering.\n\nNice If You Have\n\nExperience implementing or prototyping DSP algorithms in hardware.\n\nExperience with SOSA/VPX systems.\n\nExperience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation.\n\nExperience with porting and adapting vendor RF transceiver reference designs to FPGA evaluation boards and custom platforms.\n\nExperience with RF testing.\n\nExperience with high‑speed digital interfaces such as AXIStream, AXI‑Lite, DMA, and custom streaming buses.\n\nExperience with GPU acceleration, parallel computing, or high‑bandwidth data processing.\n\nExperience gathering requirements, shaping development roadmaps, or supporting Agile workflows.\n\nExperience with modern agile engineering workflows, including AI‑driven automation for FPGA design, simulation, synthesis, or testing.\n\nMaster's degree in Electrical Engineering, Computer Engineering, or a related field.\n\nClearance\nApplicants selected will be subject to a security investigation and may need to meet eligibility requirements for access to classified information.\n\nCompensation\nFull‑time and part‑time employees working at least 20 hours a week are eligible for Booz Allen's benefit programs. The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD). This posting will close within 90 days from the posting date.\n\nEqual Employment Opportunity\nAll qualified applicants will receive consideration for employment without regard to disability, status as a protected veteran or any other status protected by applicable federal, state, local, or international law.\n\n#J-18808-Ljbffr","datePosted":"2026-06-27T03:17:59.205Z","dateModified":"2026-06-27T03:17:59.205Z","hiringOrganization":{"@type":"Organization","name":"Phase2 Technology","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"McLean","addressRegion":"VA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"1c5d4f8c3ee36b2e55632143"},"url":"https://jobsearcher.com/jobs/1c5d4f8c3ee36b2e55632143"}}