{"schemaVersion":"jobsearcher.job.v1","id":"177bfcf22a22805ee506f8a0","url":"https://jobsearcher.com/jobs/177bfcf22a22805ee506f8a0","canonicalUrl":"https://jobsearcher.com/jobs/177bfcf22a22805ee506f8a0","title":"Substrate Layout Design Engineer","description":"Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization, speeding training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.\r\nThe company's solutions and value proposition have been widely validated by leading hyperscalers.\r\nEridu has raised over $200M to date, including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion-dollar product lines and led multiple companies to billion-dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera, Lightera, Gainspeed and Mojo Vision.\r\nEridu is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems.\r\nPosition Over\r\nJob Description\r\nWe are seeking an experienced Substrate Layout Design Engineer to support the development of an advanced multi-die organic based flip-chip module that integrates multiple dies in a chiplet format within a high-density, high-performance substrate. This role focuses on physical layout of the substrate using Siemens Xpedition tool, routing feasibility, and co-design alignment with floor planning, mechanical, and system constraints.Additionally, design of organic based substrates for SMT attachment with multilayer ABF based stack-up.The successful candidate will collaborate closely with package integration, signal/power integrity, and system mechanical teams to ensure successful layout implementation and manufacturability for a complex multi-chip package.This role is onsite in the Bay Area.\r\nDrive physical layout of high-density substrate designs for advanced multi-die packages, including planning of bump maps, netlist alignments, escape/breakout routing, via structures, and layer stack-up definition for optimum performance of signal and power connectivity.\r\nAssess routing feasibility in a co-design environment, considering die floorplans, netlist, IO bump placement, and mechanical constraints at both the component and system levels.\r\nCollaborate with system architects, packaging engineers, ASIC, SI/PI, and mechanical teams to align on floor planning strategies and package mechanical outline and structure.\r\nOptimize signal, power, and ground integrity through intelligent routing, layer usage, and design constraint enforcement.\r\nExecute DRC, DFM, and manufacturing rule checks to ensure design readiness for fabrication and assembly.\r\nGenerate and release final design packages and interface with substrate vendors for fabrication and manufacturability.\r\nSupport technical reviews of substrate layouts and iterate with internal and external stakeholders on design improvements for optimum performance.\r\nQualifications\r\n8+ years of experience in advanced substrate layout for high-performance IC packaging, with direct involvement in multi-die or chiplet-based designs.\r\nProven expertise in organic substrate layout with high routing density, fine-pitch bump escape, and constrained layer stack-ups.\r\nExperience in PCB design layout and schematic.\r\nStrong understanding of co-design methodology, including interactions between floorplan, substrate layout, and system mechanical boundaries.\r\nProficient with Siemens Xpedition, Allegro Cadence APD, design tools.\r\nFamiliarity with SI/PI design principles and how organic substrate layout impacts electrical performance.\r\nExperienced in working with OSATs or substrate suppliers for design tape-out and manufacturability validation.\r\nFamiliarity with substrate design rules and materials, substrate manufacturing.\r\nExcellent communication and documentation skills.\r\nBachelor or Master degree in Electrical, Mechanical, or Packaging Engineering, or equivalent.\r\nBenefits & Compensation\r\nJoin Us? At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.\r\nThe starting base salary for the selected candidate will be established based on relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.\r\nPay range for this role: $240,000 - $275,000 USD per year (San Francisco Bay Area).\r\nNotice to Recruiting Agencies: Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted without prior written authorization will be considered unsolicited and will become the property of Eridu.\r\nJ-18808-Ljbffr","company":"Eridu","rawCompany":"eridu","city":"Millbrae","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-06-22T01:12:04.774Z","occupations":[{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-3012.00","title":"Electrical and Electronics Drafters","slug":"electrical-and-electronics-drafters"}],"industries":[{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"333242","title":"Semiconductor Machinery Manufacturing","slug":"semiconductor-machinery-manufacturing"},{"code":"513210","title":"Software Publishers","slug":"software-publishers"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Substrate Layout Design Engineer","description":"Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization, speeding training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.\r\nThe company's solutions and value proposition have been widely validated by leading hyperscalers.\r\nEridu has raised over $200M to date, including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion-dollar product lines and led multiple companies to billion-dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera, Lightera, Gainspeed and Mojo Vision.\r\nEridu is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems.\r\nPosition Over\r\nJob Description\r\nWe are seeking an experienced Substrate Layout Design Engineer to support the development of an advanced multi-die organic based flip-chip module that integrates multiple dies in a chiplet format within a high-density, high-performance substrate. This role focuses on physical layout of the substrate using Siemens Xpedition tool, routing feasibility, and co-design alignment with floor planning, mechanical, and system constraints.Additionally, design of organic based substrates for SMT attachment with multilayer ABF based stack-up.The successful candidate will collaborate closely with package integration, signal/power integrity, and system mechanical teams to ensure successful layout implementation and manufacturability for a complex multi-chip package.This role is onsite in the Bay Area.\r\nDrive physical layout of high-density substrate designs for advanced multi-die packages, including planning of bump maps, netlist alignments, escape/breakout routing, via structures, and layer stack-up definition for optimum performance of signal and power connectivity.\r\nAssess routing feasibility in a co-design environment, considering die floorplans, netlist, IO bump placement, and mechanical constraints at both the component and system levels.\r\nCollaborate with system architects, packaging engineers, ASIC, SI/PI, and mechanical teams to align on floor planning strategies and package mechanical outline and structure.\r\nOptimize signal, power, and ground integrity through intelligent routing, layer usage, and design constraint enforcement.\r\nExecute DRC, DFM, and manufacturing rule checks to ensure design readiness for fabrication and assembly.\r\nGenerate and release final design packages and interface with substrate vendors for fabrication and manufacturability.\r\nSupport technical reviews of substrate layouts and iterate with internal and external stakeholders on design improvements for optimum performance.\r\nQualifications\r\n8+ years of experience in advanced substrate layout for high-performance IC packaging, with direct involvement in multi-die or chiplet-based designs.\r\nProven expertise in organic substrate layout with high routing density, fine-pitch bump escape, and constrained layer stack-ups.\r\nExperience in PCB design layout and schematic.\r\nStrong understanding of co-design methodology, including interactions between floorplan, substrate layout, and system mechanical boundaries.\r\nProficient with Siemens Xpedition, Allegro Cadence APD, design tools.\r\nFamiliarity with SI/PI design principles and how organic substrate layout impacts electrical performance.\r\nExperienced in working with OSATs or substrate suppliers for design tape-out and manufacturability validation.\r\nFamiliarity with substrate design rules and materials, substrate manufacturing.\r\nExcellent communication and documentation skills.\r\nBachelor or Master degree in Electrical, Mechanical, or Packaging Engineering, or equivalent.\r\nBenefits & Compensation\r\nJoin Us? At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.\r\nThe starting base salary for the selected candidate will be established based on relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.\r\nPay range for this role: $240,000 - $275,000 USD per year (San Francisco Bay Area).\r\nNotice to Recruiting Agencies: Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted without prior written authorization will be considered unsolicited and will become the property of Eridu.\r\nJ-18808-Ljbffr","datePosted":"2026-06-22T01:12:04.774Z","dateModified":"2026-06-22T01:12:04.774Z","hiringOrganization":{"@type":"Organization","name":"Eridu","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Millbrae","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"177bfcf22a22805ee506f8a0"},"url":"https://jobsearcher.com/jobs/177bfcf22a22805ee506f8a0"}}