{"schemaVersion":"jobsearcher.job.v1","id":"0f0a9771b6e7c2a5c44b4ce3","url":"https://jobsearcher.com/jobs/0f0a9771b6e7c2a5c44b4ce3","canonicalUrl":"https://jobsearcher.com/jobs/0f0a9771b6e7c2a5c44b4ce3","title":"Clocking Design Engineer","description":"Job Details:\nJob Description:\nWe are seeking a highly skilled Clocking Design Engineer to join our dynamic team.\nYou will be part of the clock team supporting Intel’s flagship CPU designs in the most advanced process nodes. In this role, you will be involved in clocking architecture definition, design and implementation of custom clock global network, development of clock tree synthesis flow, as well as custom clock circuit design and clock library cell design.\nThis is a cross-functional role that requires interfacing and collaborating with other teams such as architecture, physical design, full chip integration, RTL, circuits, validation, design automation team and EDA vendors, in a high-paced atmosphere.\nKey Responsibilities:\nImplement custom clock distribution network for high frequency flagship CPU designs\nDevelop clock tree synthesis flow and deliver custom clock solutions for high frequency flagship CPU designs\nDesign custom circuits and library cells related to clock distribution\nQualifications:\nYou must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications:\nBachelor´s degree in electrical engineering, computer engineering related STEM field and 4+ years of experience and/or Master´s degree and 3+ years of experience and/or PhD and 2+ years of experience, during which the candidate has demonstrated experience in:\nPhysical design and advanced process technologies and circuit implementation\nStatic timing analysis, clock tree synthesis, and clock-related timing parameters\nUse of industry-standard scripting and automation within EDA tool flows\nPreferred Qualifications:\n3+ years of experience in:\nBackend design and/or integration on leading edge process nodes\nHigh frequency clock distribution design and implementation, custom circuits and clock tree synthesis\nJob Type:\nExperienced Hire\nShift:\nShift 1 (United States of America)\nPrimary Location:\nUS, Texas, Austin\nAdditional Locations:\nUS, Oregon, Hillsboro\nBusiness group:\nSilicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nBenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .\n\nAnnual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD\n\nThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.\n\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.","company":"Intel","rawCompany":"intel","city":"Austin","state":"TX","isRemote":false,"isActive":false,"createdAt":"2026-04-14T10:41:33.916Z","occupations":[{"code":"17-2199.00","title":"Engineers, All Other","slug":"engineers-all-other"},{"code":"17-2061.00","title":"Computer Hardware Engineers","slug":"computer-hardware-engineers"},{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"}],"industries":[{"code":"334111","title":"Electronic Computer Manufacturing","slug":"electronic-computer-manufacturing"},{"code":"334413","title":"Semiconductor and Related Device Manufacturing","slug":"semiconductor-and-related-device-manufacturing"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"Clocking Design Engineer","description":"Job Details:\nJob Description:\nWe are seeking a highly skilled Clocking Design Engineer to join our dynamic team.\nYou will be part of the clock team supporting Intel’s flagship CPU designs in the most advanced process nodes. In this role, you will be involved in clocking architecture definition, design and implementation of custom clock global network, development of clock tree synthesis flow, as well as custom clock circuit design and clock library cell design.\nThis is a cross-functional role that requires interfacing and collaborating with other teams such as architecture, physical design, full chip integration, RTL, circuits, validation, design automation team and EDA vendors, in a high-paced atmosphere.\nKey Responsibilities:\nImplement custom clock distribution network for high frequency flagship CPU designs\nDevelop clock tree synthesis flow and deliver custom clock solutions for high frequency flagship CPU designs\nDesign custom circuits and library cells related to clock distribution\nQualifications:\nYou must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.\nMinimum Qualifications:\nBachelor´s degree in electrical engineering, computer engineering related STEM field and 4+ years of experience and/or Master´s degree and 3+ years of experience and/or PhD and 2+ years of experience, during which the candidate has demonstrated experience in:\nPhysical design and advanced process technologies and circuit implementation\nStatic timing analysis, clock tree synthesis, and clock-related timing parameters\nUse of industry-standard scripting and automation within EDA tool flows\nPreferred Qualifications:\n3+ years of experience in:\nBackend design and/or integration on leading edge process nodes\nHigh frequency clock distribution design and implementation, custom circuits and clock tree synthesis\nJob Type:\nExperienced Hire\nShift:\nShift 1 (United States of America)\nPrimary Location:\nUS, Texas, Austin\nAdditional Locations:\nUS, Oregon, Hillsboro\nBusiness group:\nSilicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.\nPosting Statement:\nAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.\nPosition of Trust\nN/A\nBenefits\nWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .\n\nAnnual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD\n\nThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.\n\nWork Model for this Role\nThis role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.","datePosted":"2026-04-14T10:41:33.916Z","dateModified":"2026-04-14T10:41:33.916Z","hiringOrganization":{"@type":"Organization","name":"Intel","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin","addressRegion":"TX","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"0f0a9771b6e7c2a5c44b4ce3"},"url":"https://jobsearcher.com/jobs/0f0a9771b6e7c2a5c44b4ce3"}}