{"schemaVersion":"jobsearcher.job.v1","id":"0bc16f595b39fc4d2dcae2cd","url":"https://jobsearcher.com/jobs/0bc16f595b39fc4d2dcae2cd","canonicalUrl":"https://jobsearcher.com/jobs/0bc16f595b39fc4d2dcae2cd","title":"STA Engineer","description":"Skills/Qualifications Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.\r\n◦ Timing closure with various timing ECO including transition, setup, hold, noise, cross talk, and power recovery.\r\n◦ Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates.\r\n◦ Synthesis Tools: Synopsys DC/DCG/FC.\r\n◦ Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus.\r\n◦ Scripting: TCL, Perl, or Python.","company":"Mirafra Technologies","rawCompany":"mirafra technologies","city":"Santa Rosa","state":"CA","isRemote":false,"isActive":false,"createdAt":"2026-05-10T01:30:49.829Z","occupations":[{"code":"17-2072.00","title":"Electronics Engineers, Except Computer","slug":"electronics-engineers-except-computer"},{"code":"17-3023.00","title":"Electrical and Electronic Engineering Technologists and Technicians","slug":"electrical-and-electronic-engineering-technologists-and-technicians"},{"code":"17-2071.00","title":"Electrical Engineers","slug":"electrical-engineers"}],"industries":[{"code":"541330","title":"Engineering Services","slug":"engineering-services"},{"code":"541512","title":"Computer Systems Design Services","slug":"computer-systems-design-services"},{"code":"334419","title":"Other Electronic Component Manufacturing","slug":"other-electronic-component-manufacturing"}],"jobPosting":{"@context":"https://schema.org","@type":"JobPosting","title":"STA Engineer","description":"Skills/Qualifications Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.\r\n◦ Timing closure with various timing ECO including transition, setup, hold, noise, cross talk, and power recovery.\r\n◦ Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates.\r\n◦ Synthesis Tools: Synopsys DC/DCG/FC.\r\n◦ Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus.\r\n◦ Scripting: TCL, Perl, or Python.","datePosted":"2026-05-10T01:30:49.829Z","dateModified":"2026-05-10T01:30:49.829Z","hiringOrganization":{"@type":"Organization","name":"Mirafra Technologies","sameAs":"https://jobsearcher.com"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Rosa","addressRegion":"CA","addressCountry":"US"}},"identifier":{"@type":"PropertyValue","name":"JobSearcher","value":"0bc16f595b39fc4d2dcae2cd"},"url":"https://jobsearcher.com/jobs/0bc16f595b39fc4d2dcae2cd"}}