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As a SOC Physical Design Engineer in NEX, you will. Perform physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
$162,041 - $259,425 a yearFull-timeExpandApply NowActive JobUpdated 3 days ago - UpvoteDownvoteShare Job
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Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
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As a member of the Logic Design and Validation group within the Lead Vehicle Development group in Design Enablement you will be part of a team that develops the RTL models and pre-silicon validation tests for test chips on the next generation Intel silicon manufacturing process.
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Experience in driving SoC digital design execution on leading edge technologies. Job Description Advanced Design is always the first design team at Intel tackling the challenges of scaling technology to the cadence of Moore's Law.
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We are looking for an SoC (System on Chip) Front-End Engineer, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry.
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Collaborate and communicates with SoC architects, microarchitects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
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We are looking for an SoC (System on Chip) Physical Design Engineer, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry.
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In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. We envision the future of computing and design for the next generation of laptop and desktop computers.
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This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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7+ years of experience in backend design and/or integration. Your responsibilities may include but not be limited to:SoC, clock design, and power delivery integrationDriving performance optimization, including co-optimization work with process teams, to create best-in-class designs.
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As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Bachelor's degree with 5 years of experience, or master's degree with 3 years of experience, in Electrical Engineering, Computer Engineering, or any STEM related field.
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Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools. Static timing analysis constraint understanding and generation, clock stamping, and timing closure. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations.
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Our bold purpose as a company is to 'create world-changing technology that enriches the lives of every person on earth' and this role is instrumental in furthering our mission to shape the future of technology.
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Multiple Power Domain analysis using standard Power Formats UPF or CPFThe ideal candidate will exhibit behavioral traits that indicate:Self-motivator with strong problem solving skills. All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Product development and delivery on leading edge process nodes. Multiple Power Domain analysis using standard Power Formats UPF or CPF. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
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Title: soc design engineer Company: Intel
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