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We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. + Proficient with System Verilog/Verilog RTL source code.
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A minimum of 2 years of experience RTL Integration, 3rd Party IP RTL through Lint, CDC check, DFT check with spyglass or VC static and generate clean reports. The ideal candidate can help along the design flow to establish synthesis runs with the related timing constraints, perform Lint, CDC, DFT checks, support regression and release process and analyze STA timing results.
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Reading and interpreting technical specs to come up with Micro-architecture and implement RTL design in System Verilog. DEG/IMSG is seeking an experienced IP Logic Design Engineer for its PCIe and Accelerator IP development organization, a dynamic team with a history of outstanding execution and industry-leading accomplishments.
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Familiar with setting up and debugging GLS runs. Accenture engineers are true Silicon to SW Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
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An experienced SoC Integration Engineer. Proficient with Synopsys Design Compiler and/or Design Compiler Ultra. If you would like to be considered for employment opportunities with Accenture and have accommodation needs for a disability or religious observance, please call us toll free at 1 (877) 889-9009, send us an email.
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A minimum 5 years of experience in Emulation, Prototyping or FPGA design and verification using System Verilog/Verilog/VHDL. Release the emulation/prototyping images to various teams doing functional validation, firmware development and design verification.
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Bachelors Degree or equivalent (12 years) work experience (If an, Associates Degree with 6 years of work experience) Inclusion and diversity are fundamental to our culture and core values. Our rich diversity makes us more innovative and more creative, which helps us better serve our clients and our communities.
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We have an unwavering commitment to diversity with the aim that every one of our people has a full sense of belonging within our organization. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users.
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Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States. Accenture is committed to providing equal employment opportunities for persons with disabilities or religious observances, including reasonable accommodation when needed.
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Experience logic designer in Verilog or VHDL and familiar with ASIC or FPGA EDA tools. Work with Research Groups, Platform Engineering teams at all layers of Hardware & Software - from FPGA BS to Firmware to OS (ESXi) to Hypervisors.
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Python, Linux)Firmware (Xilinx FPGA (MPSoC), Verilog, VHDL)CI/CD (Groovy, python, makefiles, Jenkins) Crafting new embedded software or firmware (Programmable Logic) functions.
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2+ years of professional experience designing FPGA firmware in Verilog or VHDL. Develop, test, and maintain firmware designs in Verilog and VHDL, targeting custom FPGbased avionics for space applications.
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If you would like to be considered for employment opportunities with Accenture and have accommodation needs for a disability or religious observance, please call us toll free at 1 (877) 889-9009, send us an email ( or speak with your recruiter.
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Must be a US CitizenPreferred QualificationsFamiliarity with one of the FPGA vendors (Intel, Lattice, Xilinx and Microchip)Experience with other programming languages Verilog HDL/CExperience with RTCA DO-254 complex hardware certification processExperience in code coverage, static timing, and power analysesAbility to read and follow electronic schematics.
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This position requires the development and management of Implantable Medical Device (IMD) test environments used by Firmware Verification Test (FWVT) engineers for firmware verification through simulation, emulation, timing analysis, test analysis, and logic analysis.
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