Marvell Technology

Specify a board layout topology and constraints that can be implemented by the PCB layout engineer. Simulation: HyperLynx, Ansoft SIWave and HFSS, ADS, Sigrity, PowerSI and PowerDC, and Polar stack up. Strong background in Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF applications related to IC Package and PCB Design are required.. Candidate should have experience in tools such as Sigrity, Keysight ADS, Cadence Allegro.. Equipment: Servers (Windows / Linux), scopes, traffic generators, environmental chambers, Keysight VNA/TDR

principal engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell innovates in Ethernet switching technology across a broad portfolio of segment-focused product families. Marvell switches power next-generation campus, industrial, 5G, cloud and AI networks.

What You Can Expect

The hardware application engineering position focuses on customer design enablement, bring-up, and manufacture production The engineer provides technical leadership that integrates requirements, capabilities, and functionality from customers, industry standards, electronic components, contract manufacturers, and internal quality systems. The candidate should have strong working knowledge of the major computer industry standards such as PCIe Express, Ethernet, and miscellaneous interface.

•Interface with board designers, ASIC /serdes controller designers, program management, board vendors and component vendors to fully comprehend the board design parameters

•Generate PCB stack up recommendations that comprehend the full capabilities of industry available board fabrication materials and technologies

•Specify a board layout topology and constraints that can be implemented by the PCB layout engineer

•Simulate both system level and segment levels of the design

•Perform physical correlation experiments to confirm the design

Communication And Cognitive Skills

•Complete demanding assignments by following sophisticated hardware engineering methods, tools and procedures

•Consider both the strategic and tactical aspects of solutions

•Consistently make timely decisions and balance cost and margin trade offs

•Collaborate with and influence cross-functional teams to deliver optimal solutions

•Clearly and concisely convey subtle or complex messages to a variety of audiences

•Communicate to individuals in international time zones with diverse cultural backgrounds

•Implement and follow quality procedures

•Self-monitor and report progress for project tasks

•Conduct daily activities in a manner that improves the board design team's overall effectiveness and productivity

What We're Looking For

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience.
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.

Must possess excellent written and verbal communication skills. Be able to present and clearly articulate solutions individually, and in front of medium to large groups.

Previous experience of working as an Application Engineer is a plus.

Key Requirements:

•Expertise in High Speed Ethernet Serdes interfaces : NRZ, PAM-4 100G.

•Expertise in Ethernet Physical layer (Layer 1) - Serdes, MAC, PCS including debugging L1 issues for Interop.

•Solid knowledge of electromagnetics, transmission line theory and scattering parameters

•Simulation: HyperLynx, Ansoft SIWave and HFSS, ADS, Sigrity, PowerSI and PowerDC, and Polar stack up

•PAM-4 100G Ethernet serdes interfaces

•Multi-lane cross talk analysis

•Strong background in Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF applications related to IC Package and PCB Design are required. Candidate should have experience in tools such as Sigrity, Keysight ADS, Cadence Allegro.

Experience in these areas are a plus:

•Experience with testing using TDR, VNA, Real-time and sampling scopes.

•Expertise in MATLAB and Python a plus.

•MSOffice tool suite

•Equipment: Servers (Windows / Linux), scopes, traffic generators, environmental chambers, Keysight VNA/TDR

•PCIe and OCP form factors using 8 to 14 layer stack ups

#LI-TM1

Expected Base Pay Range (USD)
137,240 - 205,600, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
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